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FEATURES Nonvolatile Memory Preset Maintains Wiper Settings Dual Channel, 256-Position Resolution Full Monotonic Operation DNL < 1 LSB 10 k , 50 k , 100 k Terminal Resistance Linear or Log Taper Settings Push-Button Increment/Decrement Compatible SPI-Compatible Serial Data Input with Readback Function 3 V to 5 V Single Supply or 2.5 V Dual Supply Operation 14 Bytes of User EEMEM Nonvolatile Memory for Constant Storage Permanent Memory Write Protection 100-Year Typical Data Retention TA = 55 C APPLICATIONS Mechanical Potentiometer Replacement Instrumentation: Gain, Offset Adjustment Programmable Voltage-to-Current Conversion Programmable Filters, Delays, Time Constants Line Impedance Matching Power Supply Adjustment DIP Switch Setting GENERAL DESCRIPTION
8-Bit Dual Nonvolatile Memory Digital Potentiometer AD5232 *
FUNCTIONAL BLOCK DIAGRAM
CS CLK SDI GND SDI SERIAL INTERFACE ADDR DECODE RDAC1 REGISTER
AD5232
VDD RDAC1 A1 W1 EEMEM1 B1
SDO WP RDY PR
SDO EEMEM CONTROL 14 BYTES USER EEMEM
RDAC2 REGISTER
RDAC2 A2 W2
EEMEM2
B2 VSS
The AD5232 device provides a nonvolatile, dual-channel, digitally controlled variable resistor (VR) with 256-position resolution. These devices perform the same electronic adjustment function as a potentiometer or variable resistor. The AD5232's versatile programming via a microcontroller allows multiple modes of operation and adjustment. In the direct program mode a predetermined setting of the RDAC register can be loaded directly from the microcontroller. Another key mode of operation allows the RDAC register to be refreshed with the setting previously stored in the EEMEM register. When changes are made to the RDAC register to establish a new wiper position, the value of the setting can be saved into the EEMEM by executing an EEMEM save operation. Once the settings are saved in the EEMEM register these values will be automatically transferred to the RDAC register to set the wiper position at system power ON. Such operation is enabled by the internal preset strobe and the preset can also be accessed externally. All internal register contents can be read out of the serial data output (SDO). This includes the RDAC1 and RDAC2 registers, the corresponding nonvolatile EEMEM1 and EEMEM2 registers, and the 14 spare USER EEMEM registers available for constant storage.
*Patent pending.
The basic mode of adjustment is the increment and decrement command controlling the present setting of the Wiper position setting (RDAC) register. An internal scratch pad RDAC register can be moved UP or DOWN one step of the nominal terminal resistance between terminals A and B. This linearly changes the wiper to B terminal resistance (RWB) by one position segment of the devices' end-to-end resistance (RAB). For exponential/logarithmic changes in wiper setting, a left/right shift command adjusts levels in 6 dB steps, which can be useful for audio and light alarm applications. The AD5232 is available in a thin TSSOP-16 package. All parts are guaranteed to operate over the extended industrial temperature range of -40C to +85C. An evaluation board is available, Part Number: AD5232EVAL.
100
PERCENT OF NOMINAL END-TO-END RESISTANCE - % RAB
75
50
25 RWB 0 RWA
0
64
128 CODE - Decimal
192
256
Figure 1. Symmetrical RDAC Operation
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2001
AD5232-SPECIFICATIONS
ELECTRICAL CHARACTERISTICS, 10 k , 50 k , 100 k
( VDD = 3 V
Parameter
VERSIONS
Min Typ1 Max Unit
10% or 5 V
10% and VSS = 0 V, VA = +VDD, VB = 0 V, -40 C < TA < +85 C unless otherwise noted.)
Symbol Conditions
DC CHARACTERISTICS RHEOSTAT MODE - Specifications Apply to All VRs Resistor Differential Nonlinearity2 R-DNL Resistor Nonlinearity2 R-INL Nominal Resistor Tolerance RAB Resistance Temperature Coefficient RAB/ T Wiper Resistance RW RW
RWB, VA = NC RWB, VA = NC IW = 100 A, VDD = 5.5 V, Code = 1EH IW = 100 A, VDD = 3 V, Code = 1EH
-1 -0.4 -40
1/2 600 5 200
+1 +0.4 +20 100
LSB % FS % ppm/C Bits LSB % FS ppm/C % FS % FS V pF pF A V V V V V V V V A pF
POTENTIOMETER DIVIDER MODE -- Specifications Apply to All VRs Resolution N Differential Nonlinearity3 DNL INL Integral Nonlinearity3 Voltage Divider Temperature Coefficient V W/ T Code = Half-Scale Full-Scale Error VWFSE Code = Full-Scale Code = Zero-Scale Zero-Scale Error VWZSE RESISTOR TERMINALS Terminal Voltage Range4 Capacitance5 Ax, Bx Capacitance5 Wx Common-Mode Leakage Current5, 6 DIGITAL INPUTS AND OUTPUTS Input Logic High Input Logic Low Input Logic High Input Logic Low Input Logic High Input Logic Low Output Logic High (SDO and RDY) Output Logic Low Input Current Input Capacitance5 POWER SUPPLIES Single-Supply Power Range Dual-Supply Power Range Positive Supply Current Programming Mode Current Read Mode Current7 Negative Supply Current Power Dissipation8 Power Supply Sensitivity5 VA,B,W CA,B CW ICM VIH VIL VIH VIL VIH VIL VOH VOL IIL CIL VDD VDD/VSS IDD IDD(PG) IDD(XFR) ISS PDISS PSS
8 -1 -0.4 -3 0 VSS
1/2 15
+1 +0.4 0 +3 VDD
f = 1 MHz, Measured to GND, Code = Half-Scale f = 1 MHz, Measured to GND, Code = Half-Scale VW = VDD/2 With Respect to GND, VDD = 5 V With Respect to GND, VDD = 5 V With Respect to GND, VDD= 3 V With Respect to GND, VDD = 3 V With Respect to GND, VDD = +2.5 V, VSS = -2.5 V With Respect to GND, VDD = +2.5 V, VSS = -2.5 V RPULL-UP = 2.2 k to 5 V IOL = 1.6 mA, VLOGIC = 5 V VIN = 0 V or VDD 2.4
45 60 0.01
1
0.8 2.1 0.6 2.0 0.5 4.9 0.4 2.5 4
VSS = 0 V VIH = VDD or VIL = GND VIH = VDD or VIL = GND VIH = VDD or VIL = GND VIH = VDD or VIL = GND, VDD = +2.5 V, VSS = -2.5 V VIH = VDD or VIL = GND VDD = 5 V 10%
2.7 2.25 0.9 3.5 35 3 3.5 0.018 0.002
5.5 V 2.75 V 10 A mA 9 mA 10 0.05 0.01 A mW %/%
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AD5232
Parameter DYNAMIC CHARACTERISTICS Bandwidth Total Harmonic Distortion
5, 9
Symbol
Conditions -3 dB, BW_10 k, R = 10 k VA = 1 V rms, VB = 0 V, f = 1 kHz, RAB = 10 k VA =1 V rms, VB = 0 V, f = 1 kHz, RAB = 50 k, 100 k VDD = 5 V, VSS = 0 V, VA = VDD, VB = 0 V, VW = 0.50% Error Band, Code 00H to 80H For RAB = 10 k/50 k/100 k RWB = 5 k, f = 1 kHz Crosstalk (CW1/CW2) CT VA = VDD, VB = 0 V, Measure VW with Adjacent VR Making Full-Scale Code Change VA1 = VDD, VB1 = 0 V, Measure VW1 with VW2 = 5 V p-p @ f = 10 kHz, Code1 = 80H; Code2 = FFH
Min
Typ1 500 0.022 0.045
Max Unit kHz % % s nV/Hz nV-s
THDW THDW
VW Settling Time Resistor Noise Voltage
tS eN_WB
0.65/3/6 9
-5
Analog Crosstalk (CW1/CW2)
CTA
-70 20 10 1 10 5 5 40 50 50 0 10 4 0 0.1 10 50 70 100 100 0.15 25
dB ns ns tCYC ns ns ns ns ns ns ns ns tCYC ns ms ms ns ns s K Cycles Years
INTERFACE TIMING CHARACTERISTICS - Applies to All Parts5, 10 Clock Cycle Time (tCYC) t1 CS Setup Time t2 CLK Shutdown Time to CS Rise t3 Input Clock Pulsewidth t 4, t 5 Clock Level High or Low From Positive CLK Transition Data Setup Time t6 Data Hold Time t7 From Positive CLK Transition CS to SDO-SPI Line Acquire t8 CS to SDO-SPI Line Release t9 CLK to SDO Propagation Delay11 t 10 RP = 2.2 k, CL < 20 pF CLK to SDO Data Hold Time t 11 RP = 2.2 k, CL < 20 pF t 12 CS High Pulsewidth12 CS High to CS High12 t 13 RDY Rise to CS Fall t 14 CS Rise to RDY Fall Time t 15 Read/Store to Nonvolatile EEMEM13 t 16 Applies to Command 2H, 3H, 9H CS Rise to Clock Rise/Fall Setup t 17 Not Shown in Timing Diagram Preset Pulsewidth (Asynchronous) tPRW Preset Response Time to RDY High tPRESP PR Pulsed Low to Refreshed Wiper Positions FLASH/EE MEMORY RELIABILITY CHARACTERISTICS Endurance14 Data Retention15
NOTES 1 Typical parameters represent average readings at 25C and VDD = 5 V. 2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper postions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. I W ~ 50 A @ VDD = 2.7 V and IW ~ 400 A @ VDD = 5 V for the R AB = 10 k version, I W ~ 50 A for the RAB = 50 k and I W ~ 25 A for the RAB = 100 k version. See Figure 13. 3 INL and DNL are measured at V W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = VDD and VB = VSS. DNL specification limits of 1 LSB maximum are Guaranteed Monotonic operating conditions. See Figure 14. 4 Resistor terminals A, B, W have no limitations on polarity with respect to each other. Dual Supply Operation enables ground-referenced bipolar signal adjustment. 5 Guaranteed by design and not subject to production test. 6 Common-mode leakage current is a measure of the dc leakage from any terminal A, B, W to a common-mode bias level of VDD/2. 7 Transfer (XFR) Mode current is not continuous. Current consumed while EEMEM locations are read and transferred to the RDAC register. See TPC 9. 8 PDISS is calculated from (I DD VDD) + (ISS VSS). 9 All dynamic characteristics use V DD = +2.5 V and VSS = -2.5 V unless otherwise noted. 10 See timing diagram for location of measured values. All input control voltages are specified with t R = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching characteristics are measured using both V DD = 3 V or 5 V. 11 Propagation delay depends on value of V DD, RPULL_UP, and C L. See applications text. 12 Valid for commands that do not activate the RDY pin. 13 RDY pin low only for instruction commands 8, 9, 10, 2, 3, and the PR hardware pulse: CMD_8 ~ 1 ms; CMD_9,10 ~ 0.12 ms; CMD_2,3 ~ 20 ms. Device operation at TA = -40C and VDD < 3 V extends the save time to 35 ms. 14 Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117 and measured at V DD = 2.7 V, TA = -40C to +85C, typical endurance at 25C is 700,000 cycles. 15 Retention lifetime equivalent at junction temperature (T J) = 55C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6eV will derate with junction temperature as shown in Figure 23 in the Flash/EE Memory description section of this data sheet. The AD5232 contains 9,646 transistors. Die size: 69 mil 115 mil, 7,993 sq. mil. Specifications subject to change without notice
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AD5232
CPHA = 1 CS
t12 t3 t2
CLK CPOL = 1
t13
t1 t5 t4 t10 t17 t11
LSB OUT
t8
SDO
t9
*
MSB
t7 t6
SDI MSB LSB
t14
RDY *NOT DEFINED, BUT NORMALLY LSB OF CHARACTER PREVIOUSLY TRANSMITTED.
t15 t16
THE CPOL = 1 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.
Figure 2a. CPHA = 1 Timing Diagram
CS
CPHA = 0
t12 t1 t2
CLK CPOL = 0
t3 t5 t17
t13
t4
t8
t10
t11 t9
SDO
MSB OUT
LSB
*
t7 t6
SDI MSB IN LSB
t14
RDY *NOT DEFINED, BUT NORMALLY MSB OF CHARACTER JUST RECEIVED.
t15 t16
THE CPOL = 0 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.
Figure 2b. CPHA = 0 Timing Diagram
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AD5232
ABSOLUTE MAXIMUM RATINGS 1
(TA = 25C, unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V, +7 V VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, -7 V VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V VA, VB, VW to GND . . . . . . . . . . . . . VSS - 0.3 V, VDD + 0.3 V AX - BX, AX - WX, BX - WX Intermittent2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 mA Digital Inputs and Output Voltage to GND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V, VDD +0.3 V Operating Temperature Range3 . . . . . . . . . . . -40C to +85C Maximum Junction Temperature (TJ Max) . . . . . . . . 150C Storage Temperature . . . . . . . . . . . . . . . . . . -65C to +150C Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220C
Package Power Dissipation . . . . . . . . . . . . . (TJ Max - TA)/ JA Thermal Resistance Junction-to-Ambient JA, TSSOP-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150C/W Thermal Resistance Junction-to-Case JC, TSSOP-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28C/W
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 3 Includes programming of nonvolatile memory.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5232 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Model AD5232BRU10 AD5232BRU10-REEL7 AD5232BRU50 AD5232BRU50-REEL7 AD5232BRU100 AD5232BRU100-REEL7
Number of Channels 2 2 2 2 2 2
End-to-End R AB (k ) 10 10 50 50 100 100
Temperature Package Package Range (C) Description Option -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 TSSOP-16 TSSOP-16 TSSOP-16 TSSOP-16 TSSOP-16 TSSOP-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16
Number of Devices per Container 96 1,000 96 1,000 96 1,000
Branding* Information 5232B10 5232B10 5232B50 5232B50 5232BC 5232BC
*Line 1 contains ADI logo symbol and the data code YYWW, line 2 contains detail model number listed in this column.
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AD5232
PIN CONFIGURATION
CLK 1 SDI 2 SDO 3 GND 4
16 RDY 15 CS 14 PR
13 WP TOP VIEW VSS 5 (Not to Scale) 12 VDD
AD5232
A1 6 W1 7 B1 8
11 A2 10 W2 9
B2
PIN FUNCTION DESCRIPTIONS
Pin Number 1 2 3
Mnemonic CLK SDI SDO
Description Serial Input Register Clock Pin. Shifts in one bit at a time on positive clock edges. Serial Data Input Pin. MSB Loaded First. Serial Data Output Pin. Open Drain Output requires external pull-up resistor. Commands 9 and 10 activate the SDO output. See Table II. Other commands shift out the previously loaded SDI bit pattern delayed by 16 clock pulses. This allows daisy-chain operation of multiple packages. Ground Pin, Logic Ground Reference. Negative Supply. Connect to zero volts for single supply applications. A Terminal of RDAC1 Wiper Terminal of RDAC1, ADDR(RDAC1) = 0H B Terminal of RDAC1 B Terminal of RDAC2 Wiper Terminal of RDAC2, ADDR(RDAC2) = 1H A Terminal of RDAC2 Positive Power Supply Pin Write Protect Pin. When active low, WP prevents any changes to the present register contents, except PR and CMD 1 and 8 will refresh RDAC register from EEMEM. Execute a NOP instruction before returning WP to logic high. Hardware Override Preset Pin. Refreshes the scratch pad register with current contents of the EEMEM register. Factory default loads midscale 80H until EEMEM is loaded with a new value by the user (PR is activated at the logic high transition). Serial Register Chip Select Active Low. Serial register operation takes place when CS returns to logic high. Ready. Active-high open drain output, requires pull-up resistor. Identifies completion of commands 2, 3, 8, 9, 10, and PR.
4 5 6 7 8 9 10 11 12 13
GND VSS A1 W1 B1 B2 W2 A2 VDD WP PR CS RDY
14
15 16
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AD5232
OPERATIONAL OVERVIEW
The AD5232 digital potentiometer is designed to operate as a true variable resistor replacement device for analog signals that remain within the terminal voltage range of VSS < VTERM < VDD. The basic voltage range is limited to a |VDD - VSS| < 5.5 V. The digital potentiometer wiper position is determined by the RDAC register contents. The RDAC register acts as a scratch pad, register allowing as many value changes as necessary to place the potentiometer wiper in the correct position. The scratch pad register can be programmed with any position value using the standard SPI serial interface mode by loading the complete representative data word. Once a desirable position is found, this value can be saved into a corresponding EEMEM register. Thereafter the wiper position will always be set at that position for any future ON-OFF-ON power supply sequence. The EEMEM save process takes approximately 25 ms, during this time the shift register is locked preventing any changes from taking place. The RDY pin indicates the completion of this EEMEM save.
SCRATCH PAD AND EEMEM PROGRAMMING
Table I. Set Two Digital POTs to Independent Data Values then Save Wiper Positions in Corresponding Nonvolatile EEMEM Registers
SDI B040H 20xxH B180H 21xxH
SDO XXXXH B040H 20xxH B180H
Action Loads 40H data into RDAC1 register, Wiper W1 moves to 1/4 full-scale position. Saves copy of RDAC1 register contents into corresponding EEMEM0 register. Loads 80H data into RDAC2 register, Wiper W2 moves to 1/2 full-scale position. Saves copy of RDAC2 register contents into corresponding EEMEM1 register.
Be aware that the PR pulse first sets the wiper at midscale when brought to logic zero, and then on the positive transition to logic high, it reloads the DAC wiper register with the contents of EEMEM. Many additional advanced programming commands are available to simplify the variable resistor adjustment process. For example, the wiper position can be changed one step at a time by using the software-controlled Increment/Decrement instruction or, by 6 dB at a time, with the Shift Left/Right instruction command. Once an Increment, Decrement, or Shift command has been loaded into the shift register, subsequent CS strobes will repeat this command. This is useful for push-button control applications. See the Advanced Control Modes description following Table I. A serial data output SDO pin is available for daisy chaining and for readout of the internal register contents. The serial input data register uses a 16-bit [instruction/address/data] WORD.
EEMEM PROTECTION
The scratch pad register (RDAC register) directly controls the position of the digital potentiometer wiper. When the scratch pad register is loaded with all zeros, the wiper will be connected to the B-Terminal of the variable resistor. When the scratch pad register is loaded with midscale code (1/2 of full-scale position), the wiper will be connected to the middle of the variable resistor. And when the scratch pad is loaded with full-scale code, all 1s, the wiper will connect to the A-Terminal. Since the scratch pad register is a standard logic register, there is no restriction on the number of changes allowed. The EEMEM registers have a program erase/write cycle limitation described in the Flash/ EEMEM Reliability section.
BASIC OPERATION
The basic mode of setting the variable resistor wiper position (programming the scratch pad register) is accomplished by loading the serial data input register with the command instruction #11, which includes the desired wiper position data. When the desired wiper position is found, the user loads the serial data input register with the command instruction #2, which copies the desired wiper position data into the corresponding nonvolatile EEMEM register. After 25 ms the wiper position will be permanently stored in the corresponding nonvolatile EEMEM location. Table I provides an application-programming example listing the sequence of serial data input (SDI) words and the corresponding serial data output appearing at the SDO pin in hexadecimal format. At system power-on, the scratch pad register is refreshed with the value last saved in the EEMEM register. The factory preset EEMEM value is midscale. The scratch pad (wiper) register can be refreshed with the current contents of the nonvolatile EEMEM register under hardware control by pulsing the PR pin.
Write protect (WP) disables any changes of the scratch pad register contents regardless of the software commands, except that the EEMEM setting can be refreshed using commands 8 and PR. Therefore, the write-protect (WP) pin provides a hardware EEMEM protection feature. Execute a NOP command before returning WP to logic high.
DIGITAL INPUT/OUTPUT CONFIGURATION
All digital inputs are ESD-protected high input impedance that can be driven directly from most digital sources. PR and WP, which are active at logic low, must be biased to VDD if they are not being used. No internal pull-up resistors are present on any digital input pins. The SDO and RDY pins are open-drain digital outputs where pull-up resistors are needed only if using these functions. A resistor value in the range of 1 k to 10 k optimizes the power and switching speed trade-off.
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AD5232
SERIAL DATA INTERFACE
VDD
The AD5232 contains a 4-wire SPI-compatible digital interface (SDI, SDO, CS, and CLK), and uses a 16-bit serial data word loaded MSB first. The format of the SPI-compatible word is shown in Table II. The chip select (CS) pin needs to be held low until the complete data word is loaded into the SDI pin. When CS returns high, the serial data word is decoded according to the instructions in Table III. The Command Bits (Cx) control the operation of the digital potentiometer. The Address Bits (Ax) determine which register is activated. The Data Bits (Dx) are the values that are loaded into the decoded register. Table IV provides an address map of the EEMEM locations. The last instruction executed prior to a period of no programming activity should be the No Operation (NOP) instruction. This will place the internal logic circuitry in a minimum power dissipation state.
PR VALID COMMAND COUNTER WP
WP
INPUT 300
AD5232
GND
Figure 4b. Equivalent WP Input Protection
DAISY CHAINING OPERATION
COMMAND PROCESSOR AND ADDRESS DECODE
5V
RPULLUP CLK SERIAL REGISTER SDO CS SDI GND
AD5232
Figure 3. Equivalent Digital Input-Output Logic
The equivalent serial data input and output logic is shown in Figure 3. The open-drain output SDO is disabled whenever chip select CS is logic high. The SPI interface can be used in two slave modes CPHA = 1, CPOL = 1 and CPHA = 0, CPOL = 0. CPHA and CPOL refer to the control bits, which dictate SPI timing in these MicroConverters(R) and microprocessors: ADuC812/ADuC824, M68HC11, and MC68HC16R1/916R1. ESD protection of the digital inputs is shown in Figures 4a and 4b.
VDD
The serial data output pin (SDO) serves two purposes. It can be used to read out the contents of the wiper setting and EEMEM values using instruction 10 and 9 respectively. The remaining instructions (#0-8, #11-15) are valid for daisychaining multiple devices in simultaneous operations. Daisy-chaining minimizes the number of port pins required from the controlling IC (see Figure 5). The SDO pin contains an open drain N-Channel FET that requires a pull-up resistor if this function is used. As shown in Figure 5, users need to tie the SDO pin of one package to the SDI pin of the next package. Users may need to increase the clock period because the pull-up resistor and the capacitive loading at the SDO-SDI interface may require additional time delay between subsequent packages. If two AD5232's are daisy-chained, 32 bits of data are required. The first 16 bits go to U2 and the second 16 bits with the same format go to U1. The 16 bits are formatted to contain the 4-bit instruction, followed by the 4-bit address, then the 8 bits of data. The CS should be kept low until all 32 bits are locked into their respective serial registers. The CS is then pulled high to complete the operation.
+V
AD5232
C SDI U1 SDO
RP 2k SDI
AD5232
U2 SDO
CS
CLK
CS
CLK
LOGIC PINS
INPUTS 300
Figure 5. Daisy-Chain Configuration Using SDO
AD5232
GND
Figure 4a. Equivalent ESD Digital Input Protection
Table II. 16-Bit Serial Data Word
MSB B14
AD5232
B13 C1
B12 C0
B11 A3
B10 A2
B9 A1
B8 A0
B7 D7
B6 D6
B5 D5
B4 D4
B3 D3
B2 D2
B1 D1
LSB D0
C3
C2
Command bits are identified as Cx, address bits are Ax, and data bits are Dx. Command instruction codes are defined in Table III.
MicroConverter is a registered trademark of Analog Devices, Inc.
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AD5232
Table III. Instruction/Operation Truth Table
Inst No. 0 1
Instruction Byte 1 B15 B8 C3 C2 C1 C0 A3 A2 A1 A0 0 0 0 0 0 0 0 1 X 0 X 0 X 0 X A0
Data Byte 0 B7 B0 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X XX XX X X X X X X
Operation No Operation (NOP). Do nothing. Write contents of EEMEM(A0) to RDAC(A0) Register. This command leaves device in the Read Program power state. To return part to the idle state, perform NOP instruction #0. SAVE WIPER SETTING. Write contents of RDAC(ADDR) to EEMEM(A0) Write contents of Serial Register Data Byte 0 to EEMEM(ADDR). Decrement 6 dB right shift contents of RDAC(A0), stops at all "Zeros." Decrement All 6 dB right shift contents of all RDAC Registers, stops at all "Zeros." Decrement contents of RDAC(A0) by "One," stops at all "Zeros." Decrement contents of all RDAC Registers by "One," stops at all "Zeros." RESET. Load all RDACs with their corresponding EEMEM previously-saved values. Write contents of EEMEM(ADDR) to Serial Register Data Byte 0. Write contents of RDAC(A0) to Serial Register Data Byte 0. Write contents of Serial Register Data Byte 0 to RDAC(A0). Increment 6 dB left shift contents of RDAC(A0), stops at all "Ones." Increment all 6 dB left shift contents of all RDAC Registers, stops at all "Ones." Increment contents of RDAC(A0) by "One," stops at all "Ones." Increment contents of all RDAC Registers "One," stops at all "Ones."
2 3 4 5 6 7 8
0 0 0 0 0 0 1
0 0 1 1 1 1 0
1 1 0 0 1 1 0
0 1 0 1 0 1 0
0
0
0
A0
X
X
X
XX
X
X
X
<< ADDR >> 0 X 0 X 0 0 X 0 X 0 0 X 0 X 0 A0 X A0 X 0
D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
9 10 11 12 13 14 15
1 1 1 1 1 1 1
0 0 0 1 1 1 1
0 1 1 0 0 1 1
1 0 1 0 1 0 1
<< ADDR >> 0 0 0 X 0 X 0 0 0 X 0 X 0 0 0 X 0 X A0 A0 A0 X A0 X
X X
X X
X X
X X
X X
X X
X X
X X
D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
NOTES 1. The SDO output shifts out the last eight bits of data clocked into the serial register for daisy-chain operation. Exception: following Instruction #9 or #10 the selected internal register data will be present in data byte 0. Instructions following #9 and #10 must be a full 16-bit data word to completely clock out the contents of the serial register. 2. The RDAC register is a volatile scratch pad register that is refreshed at power-on from the corresponding nonvolatile EEMEM register. 3. The increment, decrement, and shift commands ignore the contents of the shift register Data Byte 0. 4. Execution of the Operation column noted in the table takes place when the CS strobe returns to logic high. 5. Execution of a NOP instruction minimizes power dissipation.
REV. 0
-9-
AD5232
ADVANCED CONTROL MODES
The AD5232 digital potentiometer contains a set of user programming features to address the wide applications available to these universal adjustment devices. Key programming features include: Independently Programmable Read and Write to all registers. * Simultaneous refresh of all RDAC wiper registers from corresponding internal EEMEM registers. * Increment and Decrement instructions for each RDAC wiper register. * Left and right bit shift of all RDAC wiper registers to achieve 6 dB level changes. * Nonvolatile storage of the present scratch pad RDAC register values into the corresponding EEMEM register. * Fourteen extra bytes of user-addressable electrical-erasable memory.
Increment and Decrement Commands
Also the left shift commands were modified so that if the data in the RDAC register is greater than or equal to midscale and the data is left shifted then the data in the RDAC register is set to full-scale. This makes the left shift function as close to ideally logarithmic as is possible. The right shift #4 and #5 commands will be ideal only if the LSB is zero (i.e., ideal logarithmic-no error). If the LSB is a one then the right shift function generates a linear half LSB error, which translates to a code dependent logarithmic error for odd codes only as shown in the attached plots, (see Figure 5). The plot shows the errors of the odd codes for the AD5232.
LEFT SHIFT 0000 0000 0000 0001 0000 0010 0000 0100 0000 1000 0001 0000 0010 0000 0100 0000 1000 0000 1111 1111 1111 1111 RIGHT SHIFT 1111 1111 0111 1111 0011 1111 0001 1111 0000 1111 0000 0111 0000 0011 0000 0001 0000 0000 0000 0000 0000 0000
LEFT SHIFT (+6 dB)
RIGHT SHIFT (-6 dB)
The increment and decrement commands (#14, #15, #6, #7) are useful for the basic servo adjustment application. This command simplifies microcontroller software coding by eliminating the need to perform a readback of the current wiper position, then add one to the register contents using the microcontroller's adder. The microcontroller simply sends an increment command (#14) to the digital POT, which will automatically move the wiper to the next resistance segment position. The master increment command (#15) will move all POT wipers by one position from their present position to the next resistor segment position. The direction of movement is referenced to Terminal B. Thus each increment #15 command will move the wiper tap position farther away from Terminal B.
Logarithmic Taper Mode Adjustment
Figure 6. Detail Left and Right Shift Function for the 8-Bit AD5232
Programming instructions allow a decrement and an increment wiper position control by individual POT or in a ganged POT arrangement where both wiper positions are changed at the same time. These settings are activated by the 6 dB decrement and 6 dB increment instructions #4 and #5 and #12 and #13 respectively. For example, starting with the wiper connected to Terminal B executing nine increment instructions (#12) would move the wiper in +6 dB steps from the 0% of RBA (B terminal) position to the 100% of RBA position of the AD5232 8-Bit potentiometer. The 6 dB increment instruction doubles the value of the RDAC register contents each time the command is executed. When the wiper position is greater than midscale, the last 6 dB increment instruction will cause the wiper to go to the Full-Scale 255 code position. Any additional +6 dB instruction will no longer change the wiper position from full scale (RDAC register code = 255). Figure 6 illustrates the operation of the 6 dB shifting function on the individual RDAC register data bits for the 8-bit AD5232 example. Each line going down the table represents a successive shift operation. Very important: the left shift #12 and #13 commands were modified so that if the data in the RDAC register is equal to zero and the data is left shifted, it is then set to code 1.
Actual conformance to a logarithmic curve between the data contents in the RDAC register and the wiper position for each Right Shift #4 and #5 command execution contains an error only for the odd codes. Even codes are ideal except zero right shift or greater than half-scale left shift. The graph in Figure 7 shows plots of Log_Error [i.e., 20 x log 10 (error/code)]. For example, code 3 Log_Error = 20 x log 10 (0.5/3) = -15.56 dB, which is the worst case. The plot of Log_Error is more significant at the lower codes.
0
-10 LOG_ERROR (CODE) FOR 8-BIT -20
dB
-30
-40
-50
-60 0 20 40 60 80 100 120 140 160 180 200 220 240 260 CODE, FROM 1 TO 255 BY 2
Figure 7. Plot of Log_Error Conformance for Odd Codes Only (Even Codes Are Ideal)
-10-
REV. 0
AD5232
USING ADDITIONAL INTERNAL NONVOLATILE EEMEM
VDD
The AD5232 contains additional internal user storage registers (EEMEM) for saving constants and other 8-bit data. Table IV provides an address map of the internal nonvolatile storage registers shown in the functional block diagram as EEMEM1, EEMEM2, and bytes of USER EEMEM. Table IV. EEMEM Address Map EEMEM Address (ADDR) 0000 0001 0010 0011 0100 0101 *** 1111 EEMEM Contents of Each Device EEMEM (ADDR) AD5232 (8B) RDAC1 RDAC2 USER 1 USER 2 USER 3 USER 4 *** USER 14
A W B
VSS
Figure 8. Maximum Terminal Voltages Set by VDD and VSS
DETAIL POTENTIOMETER OPERATION
NOTES 1 RDAC data stored in EEMEM locations are transferred to their corresponding RDAC REGISTER at Power ON, or when instructions Inst#1 and Inst#8 are executed. 2 USER is internal nonvolatile EEMEM registers available to store and retrieve constants using Inst#3 and Inst#9 respectively. 3 AD5232 EEMEM locations are 1 byte each (8 bits). 4 Execution of instruction #1 leaves the device in the Read Mode power consumption state. After the last Instruction #1 is executed, the user should perform a NOP, Instruction #0 com mand to return the device to the low power idle state.
Table V. RDAC and Digital Register Address Map
Register Address (ADDR) 0000 0001
Name of Register* AD5232 (8B) RDAC1 RDAC2
The actual structure of the RDAC is designed to emulate the performance of a mechanical potentiometer. The patent-pending RDAC contains multiple strings of connected resistor segments, with an array of analog switches that act as the wiper connection to several points along the resistor array. The number of points is the resolution of the device. For example, the AD5232 has 256 connection points allowing it to provide better than 0.5% setability resolution. Figure 9 provides an equivalent diagram of the connections between the three terminals that make up one channel of the RDAC. The SWA and SWB will always be ON, while one of the switches SW(0) to SW(2N-1) will be ON one at a time depending upon the resistance step decoded from the Data Bits. The resistance contributed by RW must be accounted for in the output resistance. The SWA and SWB will always be ON while one of the switches SW(0) to SW(2 N-1) will be ON one at a time, depending upon the resistance step decoded from the Data Bits. The resistance contributed by RW must be accounted for in the output resistance.
SWA AX
*RDACx registers contain data determining the position of the variable resistor wiper.
TERMINAL VOLTAGE OPERATING RANGE
The digital potentiometer's positive VDD and negative VSS power supply defines the boundary conditions for proper three-terminal programmable resistance operation. Signals present on terminals A, B, W that exceed VDD or VSS will be clamped by a forward biased diode; see Figure 8. The ground pin of the AD5232 device is primarily used as a digital ground reference, which needs to be tied to the PCBs' common ground. The digital input logic signals to the AD5232 must be referenced to the devices' ground pin (GND), and satisfy the logic minimum input high level and the maximum low level defined in the specification table of this data sheet. An internal level-shift circuit between the digital interface and the wiper switch control ensures that the common-mode voltage range of the three-terminals A, W, and B extends from VSS to VDD.
SW(2N - 1) RDAC WIPER REGISTER AND DECODER
RS
WX SW(2N - 2)
RS
SW(1)
RS RS = RAB / 2N DIGITAL CIRCUITRY OMITTED FOR CLARITY
SW(0)
SWB
BX
Figure 9. Equivalent RDAC Structure (Patent Pending)
REV. 0
-11-
AD5232
Table VI. Nominal Individual Segment Resistor Values ( )
100
PERCENT OF NOMINAL END-TO-END RESISTANCE - % RAB
Device Resolution 8-Bit
Segment Resistor Size for RAB End-to-End Values 10 k 78.10 Version 50 k 390.5 Version 100 k 781.0 Version
75
50
PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation
The nominal resistances of the RDAC between terminals A and B are available with values of 10 k, 50 k, and 100 k. The final digits of the part number determine the nominal resistance value, e.g., 10 k = 10; 100 k = 100. The nominal resistance (RAB) of the AD5232 VR has 256 contact points accessed by the wiper terminal, plus the B terminal contact. The 8-bit data word in the RDAC latch is decoded to select one of the 256 possible settings. The general transfer equation, which determines the digitally programmed output resistance between Wx and Bx, is: RWB(Dx) = (Dx)/2 x RBA + RW
N
25 RWB 0 RWA
0
64
128 CODE - Decimal
192
256
Figure 10. Symmetrical RDAC Operation
(1)
Where N is the resolution of the VR, Dx is the data contained in the RDACx latch, and RBA is the nominal end-to-end resistance. For example, the following output resistance values will be set for the following RDAC latch codes (applies to the 8-bit, 10 k potentiometers):
Table VII. Nominal Resistance Value at Selected Codes for RAB = 10 k
Like the mechanical potentiometer the RDAC replaces, the AD5232 parts are totally symmetrical. The resistance between the wiper W and terminal A also produces a digitally controlled resistance RWA. Figure 10 shows the symmetrical programmability of the various terminal connections. When these terminals are used the B-terminal should be tied to the wiper. Setting the resistance value for RWA starts at a maximum value of resistance and decreases as the data loaded in the latch is increased in value. The general transfer equation for this operation is: RWA(Dx) = (2N-Dx)/2N x RBA + RW (2) where N is the resolution of the VR, Dx is the data contained in the RDACx latch, and RBA is the nominal end-to-end resistance. For example, the following output resistance values will be set for the following RDAC latch codes (applies to 8-bit, 10 k potentiometers).
D (DEC) 255 128 1 0
RWB (V) 10011 5050 89 50
Output State Full-Scale Midscale 1 LSB Zero-Scale*(Wiper Contact Resistance)
*Note that in the zero-scale condition a finite wiper resistance of 50 is present. Care should be taken to limit the current flow between W and B in this state to a maximum continuous value of 2 mA to avoid degradation or possible de struction of the internal switch metalization. Intermittent current operation to 20 mA is allowed.
Table VIII. Nominal Resistance Value at Selected Codes for RAB = 10 k
D (DEC) 255 128 1 0
RWA (W) 89 5050 10011 10050
Output State Full-Scale Midscale 1 LSB Zero-Scale
The multichannel AD5232 has a 0.2% typical distribution of internal channel-to-channel RBA match. Device-to-device matching is process-lot-dependent and exhibits a -40% to +20% variation. The change in RBA with temperature has a 600 ppm/C temperature coefficient.
-12-
REV. 0
AD5232
PROGRAMMING THE POTENTIOMETER DIVIDER Voltage Output Operation
The digital potentiometer easily generates an output voltage proportional to the input voltage applied to a given terminal. For example, connecting A-terminal to 5 V and B-terminal to ground produces an output voltage at the wiper which can be any value starting at zero volts up to 5 V. Each LSB of voltage is equal to the voltage applied across terminal AB divided by the 2N position resolution of the potentiometer divider. The general equation defining the output voltage with respect to ground for any given input voltage applied to terminals AB is: VW(Dx) = Dx/2N x VAB + VB (3) Operation of the digital potentiometer in the divider mode results in more accurate operation over temperature. Here the output voltage is dependent on the ratio of the internal resistors, not the absolute value; therefore, the drift improves to 15 ppm/C. There is no voltage polarity restriction between terminals A, B, and W, as long as the terminal voltage (VTERM) stays within VSS < VTERM < VDD.
OPERATION FROM DUAL SUPPLIES
The internal parasitic capacitances and the external capacitive loads dominate the ac characteristics of the RDACs. Configured as a potentiometer divider the -3 dB bandwidth of the AD5232BRU10 (10 k resistor) measures 500 kHz at half scale. Figure TPC 10 provides the large signal BODE plot characteristics of the three resistor versions 10 k, 50 k, and 100 k. A parasitic simulation model has been developed, and is shown in Figure 12. Listing I provides a macro model net list for the 10 k RDAC:
Listing I. Macro Model Net List for RDAC
.PARAM DW=255, RDAC=10E3 * .SUBCKT DPOT (A,W,B) * CA RAW CW RBW CB * .ENDS DPOT
APPLICATION PROGRAMMING EXAMPLES
A A W W B
0 W 0 B 0
{45E-12} {(1-DW/256)*RDAC+50} 60E-12 {DW/256*RDAC+50} {45E-12}
The AD5232 can be operated from dual supplies enabling control of ground-referenced ac signals. See Figure 11 for a typical circuit connection.
+2.75V VDD C GND GND SS SCLK MOSI CS CLK SDI VDD 2V p-p 1V p-p ~
The following command sequence examples have been developed to illustrate a typical sequence of events for the various features of the AD5232 nonvolatile digital potentiometer. [PCB = Printed Circuit Board containing the AD523x part]. Instruction numbers (Commands), addresses and data appearing at SDI and SDO pins are listed in hexadecimal.
AD5232
VSS
Table IX. Set Two Digital POTs to Independent Data Values
-2.5V
SDI
Figure 11. Operation from Dual Supplies
RDAC 10k A CA CA = 45pF CB CB = 45pF B
SDO XXXXH
Action Loads 40H data into RDAC2 register, Wiper W2 moves to 1/4 full-scale position. Loads 80H data into RDAC1 register, Wiper W1 moves to 1/2 Full-Scale position.
B140H
B080H
B140H
CW 60pF
W
Figure 12. RDAC Circuit Simulation Model for RDAC = 10 k
REV. 0
-13-
AD5232
Table X. Active Trimming of One POT Followed by a Save to Nonvolatile Memory (PCB Calibrate)
SDI B040H E0XXH E0XXH
SDO XXXXH B040H E0XXH
Action Loads 40H data into RDAC1 register, Wiper W1 moves to 1/4 full-scale position. Increments RDAC1 register by one to 41H, Wiper W1 moves one resistor segment away from terminal B. Increments RDAC1 register by one to 42H, Wiper W1 moves one more resistor segment away from terminal B. Continue until desired wiper position reached. Saves RDAC1 register data into corresponding nonvolatile EEMEM1 memory ADDR = 0H.
Analog Devices offers the AD5232EVAL board for sale to simplify evaluation of these programmable devices controlled by a personal computer via the printer port.
TEST CIRCUITS
Figures 13 to 22 define the test conditions used in the product specification's table.
NC DUT A W B VMS IW
NC = NO CONNECT
20XXH
E0XXH
Figure 13. Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL)
DUT A V+ B W VMS V+ = V DD 1LSB = V+/2N
EQUIPMENT CUSTOMER STARTUP SEQUENCE FOR A PCB CALIBRATED UNIT WITH PROTECTED SETTINGS
PCB setting: Tie WP to GND [prevents changes in PCB wiper set position] Power VDD and VSS with respect to GND Optional: Strobe PR pin [ensures full power ON preset of wiper register with EEMEM contents in unpredictable supply sequencing environments]
Table XI. Using Left Shift by One to Change Circuit Gain in 6 dB Steps
Figure 14. Potentiometer Divider Nonlinearity Error Test Circuit (INL, DNL)
DUT A VMS2 B VMS1 RW = [V MS1 - V MS2]/ IW W VW IW
SDI C1XXH C1XXH
SDO XXXXH XXXXH
Action Moves Wiper W2 to double the present data value contained in RDAC2 register, in the direction of the A terminal. Moves Wiper W2 to double the present data value contained in RDAC2 register, in the direction of the A terminal.
Figure 15. Wiper Resistance Test Circuit
VA V+ = V DD VDD V+ A B 10% PSRR (dB) = 20 LOG PSS (%/%) = VMS% VDD%
Table XII. Storing Additional Data in Nonvolatile Memory
~
W VMS
(
VMS VDD
)
SDI 3280H 3340H
SDO XXXXH XXXXH
Action Stores 80H data into spare EEMEM location USER1. Stores 40H data into spare EEMEM location USER2.
Figure 16. Power Supply Sensitivity Test Circuit (PSS, PSRR)
A DUT B 5V VIN OFFSET GND W OP279 VOUT
Table XIII. Reading Back Data from Various Memory Locations
~
SDI 94XXH 00XXH
SDO XXXXH XX80H
Action Prepares data read from USER3 location. Assumption: USER3 previously loaded with 80H. NOP instruction #0 sends 16-bit word out of SDO where the last 8 bits contain the contents of USER3 location. NOP command ensures device returns to idle power dissipation state.
OFFSET BIAS
Figure 17. Inverting Gain Test Circuit
-14-
REV. 0
AD5232
5V OP279 VIN OFFSET GND VOUT
~
A
Endurance quantifies the ability of the Flash/EE memory to be cycled through many Program, Read, and Erase cycles. In real terms, a single endurance cycle is composed of four independent, sequential events. These events are defined as: a. Initial page erase sequence b. Read/verify sequence c. Byte program sequence d. Second read/verify sequence During reliability qualification Flash/EE memory is cycled from 00H to FFH until a first fail is recorded, signifying the endurance limit of the on-chip Flash/EE memory.
W DUT B
OFFSET BIAS
Figure 18. Noninverting Gain Test Circuit
A VIN OFFSET GND +15V W DUT B 2.5V OP42 VOUT
~
-15V
Figure 19. Gain vs. Frequency Test Circuit
0.1V ISW CODE = OOH RSW = + B ISW VSS TO VDD _ 0.1V
As indicated in the specification pages of this data sheet, the AD5232 Flash/EE Memory Endurance qualification has been carried out in accordance with JEDEC Specification A117 over the industrial temperature range of -40C to +85C. The results allow the specification of a minimum endurance figure over supply and temperature of 100,000 cycles, with an endurance figure of 700,000 cycles being typical of operation at 25C. Retention quantifies the ability of the Flash/EE memory to retain its programmed data over time. Again, the AD5232 has been qualified in accordance with the formal JEDEC Retention Lifetime Specification (A117) at a specific junction temperature (TJ = 55C). As part of this qualification procedure, the Flash/EE memory is cycled to its specified endurance limit described above, before data retention is characterized. This means that the Flash/EE memory is guaranteed to retain its data for its full-specified retention lifetime every time the Flash/EE memory is reprogrammed. It should also be noted that retention lifetime, based on an activation energy of 0.6 eV, will derate with TJ as shown in Figure 23.
300
DUT W
Figure 20. Incremental ON Resistance Test Circuit
NC VDD DUT VSS GND A W B VCM ICM
250
NC NC = NO CONNECT
RETENTION - Years
200
Figure 21. Common-Mode Leakage Current Test Circuit
A1 A2 VDD RDAC2 RDAC1 W2 W1 B1 VSS B2
ADI TYPICAL PERFORMANCE AT TJ = 55 C
150
100
VIN
~
NC
VOUT
50
CTA = 20 log [ V OUT / V IN ]
Figure 22. Analog Crosstalk Test Circuit
Flash/EEMEM Reliability
0 40
50
60 70 80 90 TJ JUNCTION TEMPERATURE - C
100
110
The Flash/EE Memory array on the AD5232 is fully qualified for two key Flash/EE memory characteristics, namely Flash/EE Memory Cycling Endurance and Flash/EE Memory Data Retention.
Figure 23. Flash/EE Memory Data Retention
REV. 0
-15-
AD5232-Typical Performance Characteristics
2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 -0.25 -0.50 -0.75 -1.00 -1.25 -1.50 -1.75 -2.00 0 64 128 DIGITAL CODE 192 256 INL TA = +85 C INL TA = -40 C INL TA = +25 C VDD = 2.7V VSS = 0V
2000
RHEOSTAT MODE TEMPCO - ppm/ C
VDD = 5V TA = -40 C/+85 C 1500 VA = NO CONNECT RWB MEASURED
IINL ERROR - LSB
1000
500
0
0
32
64
96
128
160
192
224
256
CODE - Decimal
TPC 1. INL vs. Code, TA = -40 C, +25 C, +85 C Overlay
TPC 4. RWB/T vs. Code RAB = 10 k, VDD = 5 V
2.00 POTENTIOMETER MODE TEMPCO - ppm/ C 1.75 1.50 1.25 DNL ERROR - LSB 1.00 0.75 0.50 0.25 0 -0.25 -0.50 -0.75 -1.00 -1.25 -1.50 -1.75 -2.00 1 64 128 DIGITAL CODE 192 256 DNL T = +85 C A DNL TA = -40 C DNL TA = +25 C VDD = 2.7V VSS = 0V
70 60 50 40 30 20 10 0 -10 VDD = 5V TA = -40 C/+85 C VA = 2.00V VB = 0V
0
32
64
160 96 128 CODE - Decimal
192
224
256
TPC 2. DNL vs. Code, TA = -40 C, +25 C, +85 C Overlay
TPC 5. VWB/T vs. Code RAB = 10 k, VDD = 5 V
0.20
1 VDD = 5.5V, VSS = 0V TA = 25 C VDD = +2.5V VSS = -2.5V VCM = 0V 0.1 SEE FIGURE 21
0.15
0.10
R-DNL - LSB
0.05
0.00
-0.05 -0.10
ICM - A 0.01
0 32
64
-0.15 -0.20
96
128 160 192 224 256
CODE - Decimal
0.001 -50
-35
-20
-5
10
25
40
55
70
85
TEMPERATURE - C
TPC 3. R-DNL vs. Code RAB = 10 k, 50 k, 100 k Overlay
TPC 6. ICM vs. Temperature
-16-
REV. 0
AD5232
4
12
VDD = 5.5V
6 0 -6
f-3dB = 500kHz, R = 10k
GAIN - dB
IDD - A
f-3dB = 45kHz, R = 100k
-12 -18
2
f-3dB = 95kHz, R = 50k
-24 -30 -36 VIN = 100mV rms VDD = +2.5V, V SS = -2.5V RL = 1M TA = 25 C 1k 100k 10k FREQUENCY - Hz 1M
VDD = 2.7V
-50
-35
-20
25 40 -5 10 TEMPERATURE - C
55
70
85
-42
TPC 7. IDD vs. Temperature
TPC 10. -3 dB Bandwidth vs. Resistance
10 FILTER = 22kHz 1
THD + NOISE - %
VDD = 5V TA = 25 C
0.1 RAB = 10k
0.01
RAB = 50k , 100k
0.001 10
100
1k FREQUENCY - Hz
10k
100k
TPC 8. IDD vs. Time (Save) Program Mode
TPC 11. Total Harmonic Distortion vs. Frequency
110 100 90 80 70 60
Rw -
TA = 25 C VDD = 2.7V
50 40 30 20 10 0 1 64 128 CODE 192 256
TPC 9. IDD vs. Time Read Mode
TPC 12. Wiper On-Resistance vs. Code
REV. 0
-17-
AD5232
0 -6 -12 -18 DATA = 80 H DATA = 40 H
80 RAB = 100k RAB = 50k
PSRR REJECTION - dB
DATA = 20 H DATA = 10 H DATA = 08 H DATA = 04 H
60 RAB = 10k 40
GAIN - dB
-24 -30 -36
DATA = 02 H -42 -48 -54 -60 1k VDD = +2.7V VA VSS = -2.7V VA = 100mV rms TA = 25 C 10k 100k FREQUENCY- Hz DATA = 01 H
20 VDD = 5.5V 100mV ac VSS = 0V, VB = 5V, VA = 0V MEASURE at VW WITH CODE = 80 H TA = 25 C 10k 100k 1M
RAB = 10k 1M
0 1k
FREQUENCY - Hz
TPC 13. Gain vs. Frequency vs. Code, RAB = 10 k
0 -6 -12 -18
TPC 16. PSRR vs. Frequency
120
CTA ANALOG CROSSTALK REJECTION - dB
DATA = 80 H DATA = 40 H DATA = 20 H DATA = 10 H DATA = 08 H DATA = 04 H
100 RAB = 50k 80 RAB = 100k 60 RAB = 10k
GAIN - dB
-24 -30 -36
DATA = 02 H -42 -48 -54 -60 1k VDD = +2.7V VA VSS = -2.7V VA = 100mV rms TA = 25 C 10k 100k FREQUENCY - Hz DATA = 01 H
40
RAB = 50k 1M
VDD = V A2 = +2.75V VSS = V B2 = -2.75V VIN = +2.5VP TA = 25 C 1
SEE TEST CIRCUIT, FIGURE 22 10 FREQUENCY - kHz 100
20
TPC 14. Gain vs. Frequency vs. Code, RAB = 50 k
0 -6 -12 -18 DATA = 80 H DATA = 40 H DATA = 20 H DATA = 10 H DATA = 08 H DATA = 04 H -36 DATA = 02 H -42 -48 -54 -60 1k VDD = +2.7V VA VSS = -2.7V VA = 100mV rms TA = 25 C 10k 100k FREQUENCY - Hz DATA = 01 H
TPC 17. Analog Crosstalk vs. Frequency
GAIN - dB
-24 -30
RAB = 100k 1M
TPC 15. Gain vs. Frequency vs. Code, RAB = 100 k
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REV. 0
AD5232
DIGITAL POTENTIOMETER FAMILY SELECTION GUIDE Number of VRs Terminal Part per Voltage Number Package Range (V) AD5201 1 3, +5.5 Interface Nominal Data Resistance Control (k ) 3-wire 10, 50 Resolution (Number of Wiper Positions) 33 Power Supply Current (IDD)( A) Packages 40 SOIC-10
Comments Full ac Specs, Dual Supply, Pwr-On-Reset, Low Cost No Rollover, Pwr-On-Reset Single 28 V or Dual 15 V Supply Operation Full ac Specs, Dual Supply, Pwr-On-Reset Full ac Specs +5 V to +15 V or 5 V Operation, TC < 50 ppm/C I2C Compatible, TC < 50 ppm/C Nonvolatile Memory, Direct Program, I/D, 6 dB Settability No Rollover, Stereo, Pwr-On-Reset, TC < 50 ppm/C Full ac Specs, nA Shutdown Current Full ac Specs, Dual Supply, Pwr-OnReset, SDO Nonvolatile Memory, Direct Program, I/D, 6 dB Settability Nonvolatile Memory, Direct Program, TC < 50 ppm/C I2C Compatible, TC < 50 ppm/C +5 V to +15 V or 5 V Operation, TC < 50 ppm/C Full ac Specs, nA Shutdown Current Nonvolatile Memory, Direct Program, I/D, 6 dB Settability Full ac Specs, Dual Supply, Pwr-On-Reset Full ac Specs, nA Shutdown Current Full ac Specs, Dual Supply, Pwr-On-Reset
AD5220 1 AD7376 1
5.5 15 , +28 3 , +5.5
UP/ DOWN 3-wire
10, 50, 100
128
40 100
10, 50, 100, 1000 128
AD5200 1
3-wire
10, 50
256
40
PDIP, SO-8, SOIC-8 PDIP-14, SOL-16, TSSOP-14 SOIC-10
AD8400 1 AD5260 1
5.5 5, +15 3, +5.5 2.75, +5.5 3, +5.5
3-wire 3-wire
1, 10, 50, 100 20, 50, 200
256 256
5 60
SO-8 TSSOP-14
AD5241 1 AD5231 1
2-wire 3-wire
10, 100, 1000 10, 50, 100
256 1024
50 10
SO-14, TSSOP-14 TSSOP-16
AD5222
2
UP/ DOWN 3-wire 3-wire
10, 50, 100, 1000 128
80
SO-14, TSSOP-14 PDIP, SO-14, TSSOP-14 TSSOP-14
AD8402 2 AD5207 2
5.5 3, +5.5 2.75, +5.5 2.75, +5.5 3, +5.5 5, +15
1, 10, 50, 100 10, 50, 100
256 256
5 40
AD5232 2
3-wire
10, 50, 100
256
10
TSSOP-16
AD5235* 2
3-wire
25, 250
1024
20
TSSOP-16
AD5242 2 AD5262* 2
2-wire 3-wire
10, 100, 1000 20, 50, 200
256 256
50 60
SO-16, TSSOP-16 TSSOP-16
AD5203 4 AD5233 4
5.5 2.75, +5.5 3, +5.5
3-wire 3-wire
10, 100 10, 50, 100
64 64
5 10
PDIP, SOL-24, TSSOP-24 TSSOP-16
AD5204 4
3-wire
10, 50, 100
256
60
PDIP, SOL-24, TSSOP-24 PDIP, SOL-24, TSSOP-24 PDIP, SOL-24, TSSOP-24
AD8403 4 AD5206 6
5.5 3, +5.5
3-wire 3-wire
1, 10, 50, 100 10, 50, 100
256 256
5 60
*Future Product, consult factory for latest status. Latest Digital Potentiometer Information located at: www.analog.com/DigitalPotentiometers
REV. 0
-19-
AD5232
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead TSSOP (RU-16)
0.201 (5.10) 0.193 (4.90)
16
9
0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25)
1 8
PIN 1 0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) MAX
SEATING PLANE
8 0.0256 (0.65) 0.0118 (0.30) 0.0079 (0.20) 0 BSC 0.0075 (0.19) 0.0035 (0.090)
0.028 (0.70) 0.020 (0.50)
-20-
REV. 0
PRINTED IN U.S.A.
C02618-1-10/01(0)

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